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Add RVC HINT/RES/NSE encs & rework disassembly #56

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merged 1 commit into from
Jan 9, 2025

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elliotb-lowrisc
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Add explicit HINT, Reserved, and NSE compressed instruction encodings from the spec.
This allows Templates to more easily specify these special encodings and enables more accurate disassembly.
Note that some encodings overlap.

Add new instruction disassembly pretty printer functions for special cases where the operands are uninteresting or ambiguous.

Rework the disassembly to account for overlapping encodings. Use XLEN, when available, and carful ordering to distinguish overlapping encodings from each other.
Present both encodings when encodings overlap and XLEN is not available.

Integrate new disassembly so that XLEN will be passed through when known (currently only for RVFI V2 packets).

Minor errors may remain.
Caution only goes so far when there are so many fiddly changes required.

Add explicit HINT, Reserved, and NSE compressed instruction
encodings from the spec.
This allows Templates to more easily specify these special encodings
and enables more accurate disassembly.
Note that some encodings overlap.

Add new instruction disassembly pretty printer functions
for special cases where the operands are uninteresting or ambiguous.

Rework the disassembly to account for overlapping encodings.
Use XLEN, when available, and carful ordering to distinguish
overlapping encodings from each other.
Present both encodings when encodings overlap and XLEN is not available.

Integrate new disassembly so that XLEN will be passed through when known
(currently only for RVFI V2 packets).

Minor errors may remain.
Caution only goes so far when there are so many fiddly changes required.
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@marnovandermaas marnovandermaas left a comment

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Thanks for putting this together. Very useful work! Do you have any instructions on how to test this PR?

@elliotb-lowrisc
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No tests currently use the new instructions, but you can try out the new disassembly using something like:

make QCVEngine
utils/scripts/runTestRIG.py -a sail -b sail -r rv32ic --test-include-regex "^compress" -v3 -n2 

Note that a generic disassembly will be used for the plain instruction listing at the end, but a more precise (XLEN-aware) disassembly will be output when the RVFI packets are being compared.

@elliotb-lowrisc
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@PeterRugg I'm not sure how this fits in with your ongoing work, but hopefully it can be of some use.

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@elliotb-lowrisc Thanks so much for this and sorry for missing it for so long. I've looked through but not checked all the details, but I'm sure it's much better than it was.

@PeterRugg PeterRugg merged commit 56a761e into CTSRD-CHERI:master Jan 9, 2025
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@elliotb-lowrisc elliotb-lowrisc deleted the rvc_2 branch January 10, 2025 09:59
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No worries, glad to help 👍

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3 participants